The present invention relates to electronic circuits, and more particularly to adjustment of phase in high-speed clock and data recovery systems.
The increasing speed with which multiple types of data, such as text, audio and video, are transported over existing communication networks has brought to the fore the reliability with which such data transportation is carried out. In accordance with one conventional method, to ensure reliable data transfer, the data is first encoded with a reference clock signal at the transmitting end of the network to generate a composite signal. Thereafter, the composite signal is transmitted over the network to the receiving end. At the receiving end, the data and clock signals are recovered from the composite signal to ensure that the data and clock signals remain synchronous with respect to each other.
The clock and data recovery is typically carried out, for example, by a delay locked loop or a phase locked loop. In operation, a phase locked loop maintains a fixed relationship between the phase of the signal it receives and the phase of the signal it generates. FIG. 1 is a simplified block diagram of a conventional phase locked loop 10 adapted to extract the data and clock signals from composite signal Comp. Phase locked loop (PLL) 10 includes, among other components, phase detector 12, charge pump 14, loop filter 16, voltage controlled oscillator (VCO) 18 and flip-flop 20. The extracted clock signal Clk is supplied at the output terminal of VCO 18. Signals Clk and Comp are respectively applied to CK and D input terminal of flip-flop 20. Signal Data generated at the output terminal of flip-flop 20 is the data extracted form signal Comp. Once in a locked state, the phase of signal Clk generated by PLL 10 is locked to that of signal Comp received by PLL 10. The operation of PLL 10 is described further below.
Phase detector 12 receives signals Comp and Clk, and in response, generates signal A that corresponds to the difference between the phases of these two signals. Charge pump 14 receives signal A and in response generates current signal B whose magnitude varies depending on the magnitude of signal A. Loop filter 16 filters out the high frequency components of signal B and delivers the filtered-out signal to VCO 18.
If signal Comp leads signal Clk in phase—indicating that the VCO is running relatively slowly—signal A causes charge pump 14 to increase its output current I until VCO 18 achieves an oscillation frequency at which signal Clk is phase-locked with signal Comp. If, on the other hand, signal Comp lags signal Clk in phase—indicating that the VCO is running relatively fast—signal A causes charge pump 14 to reduce its output current B until VCO 18 achieves an oscillation frequency at which signal Clk is phase-locked with signal Comp.
FIG. 2 shows the current I generated by charge pump 14 versus the phase difference θe between signals Comp and Clk of FIG. 1. Ideally, when signal Clk is phase-locked with signal Comp, i.e., when θe is zero, current I generated by charge pump 14 is desired to be zero. Furthermore, ideally the magnitude of current I is desired to reach its highest value when θe is ±180°. The I-θe line for such an ideal PLL is designated with reference numeral 30. However, most PLLs exhibit non-ideal characteristics. Accordingly, for example, in PLL 10 current I is non-zero when θe is zero or vice versa, as shown by the I-θe line 35. This non-ideal shift in I-θe may reduce the noise immunity of PLL 10. Consequently, if PLL 10 is deployed in long-haul applications, in which case signal Comp delivered to PLL 10 is often noisy and distorted, the reduce noise immunity of PLL 10 may introduce instabilities in the phase relationship between signals Comp and Clk that, in turn, may violate the set-up time and hold time of flip-flop 20.
FIG. 3 is a simplified block diagram of a prior art PLL 40 that is adapted to partly overcome the above mentioned problems associated with PLL 10. PLL 40 includes, in part, an adjustable delay element 52 that receives the external signal Phase_adjust to adjust the phase of signal Clk before it is applied to flip-flop 50. The amount of delay of signal Clk through adjustable delay element 52 is varied by varying the value of signal Phase_adjust during a jitter tolerance test. During this test, a user deliberately introduces jitter and noise into signal Comp while at the same time continuously varying signal Phase_adjust until the tolerable limit of jitter is reached. In other words, signal Phase_adjust is varied until the maximum allowed error rate in the extracted data is reached. Signal Phase_adjust may be an analog signal or a digital signal, depending on the implementation of adjustable delay element 52.
Referring to FIG. 3, in some applications, the extracted clock signal Clk is required to operate at relatively very high frequencies, such as 10 GHz. Operating the clock signal Clk at such high frequencies causes a number of problems. First, adjusting the delay of a signal running at 10 GHz poses a challenging task. Second, the higher the operating frequency of a circuit, the greater is its power consumption. To accommodate the relatively higher power consumption, larger transistor sizes are required and thus greater semiconductor surface area is consumed which, in turn, increases the cost. Third, the higher the frequency, the greater is the current flow across parasitic capacitances. For example, the high frequency creates coupling between source/drain and the substrate regions of, e.g., MOS transistors used in adjustable delay circuit 52. This coupling may increase the noise coupling (i.e., cross-talk) between adjacent circuit blocks.
It is desired to have a Phase_adjustment technique which does not suffer from the high frequency related problems described above.